Prior art methods for programming a floating gate memory cell, such as are used in EPROM, EEPROM, and flash EEPROM devices, utilize hot electron injection from the channel to the floating gate. During such programming, both the control gate voltage and the drain voltage are at high potential in order to create hot electrons in the channel and inject the hot electrons into floating gate.
When prior art programming methods are used, after electrically erasing the cells, to program a floating gate memory cell, a programming speed degradation is seen. The degradation represents a slowdown of programming after electrically erasing the cells. The degree of degradation depends on the degree the cells are erased, as shown by the data in Table 1.
TABLE 1 ______________________________________ ERASE CELL VOLT- V.sub.T PROGRAMMING TIME AGE and I.sub.D 0 5 .mu.s 10 .mu.s 20 .mu.s 30 .mu.s 50 .mu.s 70 .mu.s ______________________________________ 13V V.sub.T (V) 2.36 7.10 8.42 9.33 I.sub.D (.mu.A) 24.80 0 0 0 15V V.sub.T (V) 2.01 2.27 7.89 9.09 I.sub.D (.mu.A) 45.10 29.09 0 0 17V V.sub.T (V) 1.80 1.81 1.84 2.10 9.65 I.sub.D (.mu.A) 56.36 50.06 44.58 39.43 0 19V V.sub.T (V) 1.68 1.69 1.69 1.70 1.71 1.76 8.59 I.sub.D (.mu.A) 61.38 61.14 60.96 60.46 60.02 58.11 0 ______________________________________
Degradation of programming speed is seen in both types of cells used in flash EEPROM technology: (1) The split gate cell as described in U.S. patent application Ser. No. 204,175 filed by Harari and entitled, "Highly Compact EPROM and Flash EEPROM Devices" and (2) The single transistor cell or EPROM-like cell as described by Kume et al. in "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure", 560IEDM87, IEEE, 1987. The physical phenomena behind this degradation is the decrease of maximum value of channel longitudinal electrical field, for the same programming conditions, after electrically erasing the cell. The degradation is more pronounced in the split gate cell because of greater sensitivity of the longitudinal electrical field to the potential of the floating gate after electrical erasure.
To better understand the cause of programming speed degradation after electrically erasing a split gate cell, FIGS. 1a and 1b show the status of the floating gate after erase. Cell 100a in FIG. 1a is moderately erased and cell 100b in FIG. 1b is strongly erased, which is often referred to as "overerased." In moderately erased cell 100a (FIG. 1a) at the end of erasure floating gate 101a is neutral or has only a slight positive charge. In overerased cell 100b (FIG. 1b) floating gate 101b is depleted of electrons at the end of erasure and thus the floating gate is positively charged. This positive charge increases the floating gate potential by an amount equal to Q/C.sub.TOT where Q is the total positive charge on floating gate 101b and C.sub.TOT is the total coupling capacitances to the floating gate C.sub.TOT =C.sub.1 +C.sub.2 +C.sub.D making the floating gate more positive compared with moderately erased cell 101a (FIG. 1a).
The conductance of channel 102b under floating gate 101b for overerased cell 100b is greater than the conductance of moderately erased cell 101a for the same programming conditions, i.e., the same control gate voltage V.sub.CG and drain voltage VD during programming. Depending on the degree of overerasure, the conductance of channel 102b under floating gate 101b becomes comparable or even higher than the conductance of the channel of select transistor 103b under programming biasing conditions. Because of this high conductance of channel 102b under the floating gate 101b, the maximum electrical field in channel 102b for overerased cell 100b in FIG. 1b is lower than the maximum electrical field in channel 102a of moderately erased cell 100a in FIG. 1a, and thus, for the same programming conditions (e.g., control gate voltage V.sub.CG =12 V, drain voltage V.sub.D =7 V), moderately erased cell 100a of FIG. 1a programs faster than overerased cell 100b of FIG. 1 b. This means that overerased cells program slower.
The conclusion that overerased cells program slower is supported also by considering floating gate current I.sub.FG vs. floating gate voltage V.sub.FG characteristic shown in FIG. 2. The curve of FIG. 2 is taken from a test cell identical in geometry with a floating gate cell of interest, but where the floating gate is electrically contacted to allow measurements to be made. The I.sub.FG vs V.sub.FG characteristic in FIG. 2 is the well-known bell gate current characteristic of a MOS transistor. If in a moderately erased cell 100a the floating gate potential at the beginning of programming is approximately V.sub.FGA (see FIG. 2), the floating gate potential of overerased cell 100b, V.sub.FGB, is greater than V.sub.FGA by the amount Q/C.sub.TOT Depending on the amount of overerasure, the floating gate current in overerased cells can be very small at the beginning of programming (corresponding to V.gtoreq.V.sub.FGB in FIG. 2). Therefore, cells with V.sub.FG .gtoreq.V.sub.FGB program very slowly because the floating gate current at the beginning of programming is very small.
From FIG. 2 it is clear that, for fast programming, the erase has to be controlled such that after erase the floating gate potential under programming biasing conditions is approximately V.sub.FGA, where the floating gate current during programming is relatively high. Unfortunately electrical erase is not a self-limiting mechanism, i.e., the erase continues (with a different speed) as long as the erase voltage is applied. This means that in order to control the amount of cell erasure, the erase time and erase voltage have to be controlled.
Attempts have made in the prior art to control the amount of cell erasure. For example, "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure," 560-IEDM87, IEEE, 1987 describes an EEPROM Cell having asymmetrical source and drain regions in an attempt to provide a high degree of control during erase. U.S. Pat. No. 4,794,856, issued Jan. 10, 1989, describes a self-limiting technique for preventing overerasure wherein a drain voltage is fed back to a floating gate to reduce the electric field across the tunnel oxide. However, even using techniques known in the prior art in order to erase a plurality of cells having non-uniform programming levels and erase characteristics, it is difficult to ensure a narrow distribution of cell characteristics or threshold voltage after erasure. Furthermore, each cell's erase characteristics change with programming/erase cycling due to electron trapping into oxide through which erase is performed. This distribution in erase characteristics of a population of cells, and changes in the distribution with the number of program/erase cycles, makes more difficult the control of the amount of cell erasure. Even using sophisticated methods to control erasing, there will be a distribution of the amount of erasure among cells, and as a consequence there will be a distribution in programming speed after electrically erasing the cells.
An "8k EEPROM using the SIMOS storage cell", Burkhard Giebel, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June 1980, pps. 311-315, describes a floating gate EEPROM device which programs by channel hot electron injection and is electrically erased through Fowler-Nordheim tunneling between the floating gates and an auxiliary N+ junction. Each cell includes a single polycrystalline silicon MOS transistor in series with a double polycrystalline silicon floating gate memory transistor. The single polycrystalline silicon MOS transistor serves as a select transistor in order to prevent leakage in overerased cells. Overerasure slows programming. To speed programming, Giebel describes a two-step programming method. In the first step, the control gate is held at 15 volts and in the second step the control gate is held at 25 volts. In both steps the gate of the select transistor is held high at 20 volts. The Giebel structure does not utilize a split gate cell, and the presence of N+ junctions between Giebel's memory transistor and select transistor causes the device to have an I.sub.FG versus V.sub. FG characteristic which does not include a hump L.sub.2 as shown in FIG. 3 for a split gate cell, but rather is the bell-shaped characteristic depicted in FIG. 2. Thus, the more a Giebel cell is overerased, the smaller the floating gate current is during programming, in contrast to the case with split gate cells having the characteristic depicted in FIG. 3, in which greater amounts of overerasure yields greater amounts of floating gate current during programming, in certain programming conditions described in this invention.